1. Field of the Invention
The present invention relates to techniques for improving computer system performance. More specifically, the present invention relates to a method and an apparatus for using knowledge gained during the compilation process to control cache line eviction during program execution.
2. Related Art
Advances in semiconductor fabrication technology have given rise to dramatic increases in microprocessor clock speeds. This increase in microprocessor clock speeds has not been matched by a corresponding increase in memory access speeds. Hence, the disparity between microprocessor clock speeds and memory access speeds continues to grow. This causes performance problems because microprocessor systems often spend a large fraction of time waiting for memory references to complete instead of performing computational operations.
In order to alleviate this performance problem, modern computer systems include one or more levels of faster cache memory to reduce the time required to access instructions and data. During computer system operation, when a central processing unit (CPU) requires new instructions or data, a request is sent to the cache. If the instructions or data are available within the cache, the CPU accesses them from the cache. If, however, the instructions or data are not available in the cache, a cache miss occurs, which causes a cache line containing the instructions or data to be loaded into the cache from the computer system's main memory.
When the cache is full, a cache line must be evicted from the cache prior to loading a new cache line. Many schemes are used to determine the best cache line to evict. The objective of these schemes is to evict the cache line that will not be needed for the greatest amount of time. Most computer systems use a variation of the least recently used (LRU) replacement scheme, which evicts the cache line that is “least recently used.” The LRU replacement scheme generally works because accesses to instructions and data tend to exhibit a large amount of temporal locality. This means that more recently accessed instructions and data are most likely to be accessed again.
However, the LRU replacement scheme does not work well when a cache line containing only scratch data (that will be used only once) is loaded into the cache. In these cases, the computer system has no way of knowing that the data will be used only once and will never be accessed again. However, an LRU eviction scheme will retain the cache line containing scratch data until it becomes the least recently used cache line, and will instead evict other cache lines containing data that will be accessed again, thereby decreasing system performance.
Hence, what is needed is a method and apparatus for controlling cache line eviction without the problems described above.